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DDR5 controller IP

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Compare 84 IP from 10 vendors (1 - 10)
  • DDR5 Memory Controller IP with Advanced Feautures
    • Supports DDR5 protocol standard JESD79-5 Specification.
    • Compliant with DFI version 5.0 Specification.
    • Supports up to 16 AXI ports with data width upto 512 bits.
    • Supports controllable outstanding transactions for AXI write and read channels
  • DDR5 Controller IP
    • Supports DDR5 protocol standard JESD79-5 Specification.
    • Compliant with DFI version 5.0 Specification.
    • Supports up to 16 AXI ports with data width upto 512 bits.
    • Supports controllable outstanding transactions for AXI write and read channels
  • DDR Secure Controller supporting DDR5
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
    • Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
    Block Diagram -- DDR Secure Controller supporting DDR5
  • DDR Low Latency Controller supporting DDR5
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
    • Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
    Block Diagram -- DDR Low Latency Controller supporting DDR5
  • DDR Controller supporting DDR5 with Advanced Features Package
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
    • Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
    Block Diagram -- DDR Controller supporting DDR5 with Advanced Features Package
  • DDR Controller supporting DDR5 with a CHI interface and Advanced Feature Package
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
    • Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
    Block Diagram -- DDR Controller supporting DDR5 with a CHI interface and Advanced Feature Package
  • DDR Controller supporting DDR5 MRDIMM Gen2 with Advanced Features Package
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
    • Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
    Block Diagram -- DDR Controller supporting DDR5 MRDIMM Gen2 with Advanced Features Package
  • DDR Controller supporting DDR5 and DDR4 with Advanced Features Package
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
    • Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
    Block Diagram -- DDR Controller supporting DDR5 and DDR4 with Advanced Features Package
  • DDR Controller supporting DDR5 and DDR4 with a CHI interface and Advanced Feature Package
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
    • Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
    Block Diagram -- DDR Controller supporting DDR5 and DDR4 with a CHI interface and Advanced Feature Package
  • DDR Controller supporting DDR5 and DDR4 with a CHI interface
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
    • Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
    Block Diagram -- DDR Controller supporting DDR5 and DDR4 with a CHI interface
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