ARC HS4x processor IP
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ARC HS68 64-bit, dual-issue processor with MMU, ARCv3 ISA, for embedded Linux applications
- Dual-issue, 64-bit processors for high-performance embedded applications
- 52-bit physical and 64-bit virtual addressing
- Up to 5400 DMIPS and 11,088 CoreMark per core at 1.8 GHz on 16FFC (worst case conditions, single-core configuration
- Multicore Processor versions with up to 12 CPU cores and up to 16 hardware accelerators
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ARC HS66 64-bit, dual-issue processor core, interconnect, ARCv3 ISA, for embedded applications
- Dual-issue, 64-bit processors for high-performance embedded applications
- 52-bit physical and 64-bit virtual addressing
- Up to 5400 DMIPS and 11,088 CoreMark per core at 1.8 GHz on 16FFC (worst case conditions, single-core configuration
- Multicore Processor versions with up to 12 CPU cores and up to 16 hardware accelerators
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ARC HS48 32-bit, dual-issue processor with MMU, ARCv2 ISA, for embedded Linux applications
- Dual-issue, 32-bit processor for high-performance embedded applications
- Deliver up to 5700 DMIPS and 9880 CoreMark per core at 1.9 GHz on 16ff (worst case conditions, single-core configuration)
- 3.0 DMIPS/MHz, 5.2 CoreMarks/ MHz (per core)
- Based on advanced ARCv2 ISA
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ARC HS46 32-bit, dual-issue processor core, ARC V2 ISA, for embedded applications
- Dual-issue, 32-bit processor for high-performance embedded applications
- Deliver up to 5700 DMIPS and 9880 CoreMark per core at 1.9 GHz on 16ff (worst case conditions, single-core configuration)
- 3.0 DMIPS/MHz, 5.2 CoreMarks/ MHz (per core)
- Based on advanced ARCv2 ISA
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ARC HS44 32-bit, dual-issue processor core, ARC V2 ISA, for embedded applications
- Dual-issue, 32-bit processor for high-performance embedded applications
- Deliver up to 5700 DMIPS and 9880 CoreMark per core at 1.9 GHz on 16ff (worst case conditions, single-core configuration)
- 3.0 DMIPS/MHz, 5.2 CoreMarks/ MHz (per core)
- Based on advanced ARCv2 ISA
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ARC HS68MP multi-core version of dual-issue HS68 processor with MMU, ARCv3 ISA, for embedded Linux applications
- Dual-issue, 64-bit processors for high-performance embedded applications
- 52-bit physical and 64-bit virtual addressing
- Up to 5400 DMIPS and 11,088 CoreMark per core at 1.8 GHz on 16FFC (worst case conditions, single-core configuration
- Multicore Processor versions with up to 12 CPU cores and up to 16 hardware accelerators
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ARC HS48x2 dual-core version of dual-issue HS48 processor with MMU, ARCv2 ISA, for embedded Linux applications
- Dual-issue, 32-bit processor for high-performance embedded applications
- Deliver up to 5700 DMIPS and 9880 CoreMark per core at 1.9 GHz on 16ff (worst case conditions, single-core configuration)
- 3.0 DMIPS/MHz, 5.2 CoreMarks/ MHz (per core)
- Based on advanced ARCv2 ISA
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ARC HS48x4 is quad-core version of dual-issue HS48 processor with MMU, ARCv2 ISA, for embedded Linux applications
- Dual-issue, 32-bit processor for high-performance embedded applications
- Deliver up to 5700 DMIPS and 9880 CoreMark per core at 1.9 GHz on 16ff (worst case conditions, single-core configuration)
- 3.0 DMIPS/MHz, 5.2 CoreMarks/ MHz (per core)
- Based on advanced ARCv2 ISA
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Optimized for GHz+ operating speeds with minimum area and power consumption, ARC HS Processors are ideal for very high-performance embedded applications
- ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
- ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
- Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.
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Scalar and SIMD floating point option for the ARC HS5x, HS5xD and HS6x processors
- Dual-issue, 64-bit processors for high-performance embedded applications
- 52-bit physical and 64-bit virtual addressing
- Up to 5400 DMIPS and 11,088 CoreMark per core at 1.8 GHz on 16FFC (worst case conditions, single-core configuration
- Multicore Processor versions with up to 12 CPU cores and up to 16 hardware accelerators
