AI Inference IP
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AI inference processor IP
- High Performance, Low Power Consumption, Small Foot Print IP for Deep Learning inference processing.
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AI Inference IP. Ultra-low power, tiny, std CMOS. ~ 100K parameter RNN
- Ultra Low power
- Standard CMOS
- Small area
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AI Accelerator (NPU) IP - 3.2 GOPS for Audio Applications
- 3.2 GOPS
- Ultra-low <300uW power consumption
- Low latency
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AI Accelerator: Neural Network-specific Optimized 1 TOPS
- Performance efficient 18 TOPS/Watt
- Capable of processing real-time HD video and images on-chip
- Advanced activation memory management
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AI Accelerator Specifically for CNN
- A specialized hardware with controlled throughput and hardware cost/resources, utilizing parameterizeable layers, configurable weights, and precision settings to support fixed-point operations.
- This hardware aim to accelerate inference operations, particulary for CNNs such as LeNet-5, VGG-16, VGG-19, AlexNet, ResNet-50, etc.
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Highly scalable inference NPU IP for next-gen AI applications
- Matrix Multiplication: 4096 MACs/cycles (int 8), 1024 MACs/cycles (int 16)
- Vector processor: RISC-V with RVV 1.0
- Custom instructions for softmax and local storage access
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High performance-efficient deep learning accelerator for edge and end-point inference
- Configurable MACs from 32 to 4096 (INT8)
- Maximum performance 8 TOPS at 1GHz
- Configurable local memory: 16KB to 4MB
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RISC-V-based AI IP development for enhanced training and inference
- RISC-V-based AI IP development for enhanced training and inference.
- Silicon-proven solutions tailored for AI workload optimization.
- Energy-efficient performance with industry-leading Perf/W.
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AI Accelerator
- Independent of external controller
- Accelerates high dimensional tensors
- Highly parallel with multi-tasking or multiple data sources
- Optimized for performance / power / area
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NPU IP for Embedded AI
- Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
- Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
- Future proof architecture that supports the most advanced ML data types and operators
