AES crypto engine IP
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25
IP
from 5 vendors
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10)
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AES Multi-purpose crypto engine
- ASIC and FPGA
- Supports a wide selection of programmable ciphering modes based on NIST SP 800-38:
- Masking option available with excellent protection against SPA & DPA
- Context switching
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SM4-GCM Multi-Booster crypto engine
- ASIC & FPGA
- High throughput
- Guaranteed performance with small packets
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AES-GCM Ultra-low latency crypto engine
- High throughput: 64 GB/s (512 Gbps)
- Ultra-low latency
- Optional CRC support for data integrity
- 128-bit and 256-bit key
- NIST SP 800-38D compliant
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Inline cipher engine with AXI, for memory encryption
- Throughput: 128 bit (16 Byte) wide encryption/decryption per cycle
- Throughput: 1 tweak computation per 4 clock cycles
- Bidirectional design including arbitration between read and write requests
- Zero clock overhead for switching between encryption (write) and decryption (read)
- 30-40 cycle data channel latency
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ChaCha20 DPA Resistant Crypto Accelerator
- Quicken time-to-market using precertified DPA Countermeasures
- Highly secure cryptographic engine primitives
- Extensive validation using the Test Vector Leakage Assessment (TVLA) methodology (revealing no leakage beyond 100 million traces)
- Cores protected against univariate first- and second-order side-channel attacks beyond 1 billion operations
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Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
- Protocol aware IPsec, SSL, TLS, DTLS, 3GPP and MACsec Packet Engine with virtualization, caches classifier and Look-Aside interface for multi-core application processors
- 5-10 Gbps, programmable, maximum CPU offload by classifier, supports new and legacy crypto algorithms, AMBA interface
- Supported by Driver development kit, QuickSec IPsec toolkit, Linaro ODP, DPDK, Linux Crypto
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AES XTS/GCM Accelerators
- Wide bus interface
- Basic AES encrypt and decrypt operations
- Key sizes: 128, 192 and 256 bits
- Key scheduling in hardware, allowing key, key size and direction changes every 13/15/17 clocks with zero impact on throughput
- Hardware reverse (decrypt) key generation
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Multi-Protocol Engine with Classifier, Inline and Look-Aside, 10-100 Gbps
- Protocol aware IPsec, SSL, TLS, DTLS, 3GPP, MACsec packet engine with classifier and in-line interface for multi-core server processors
- 10-100 Gbps, programmable, maximum CPU offload by classifier, supports new and legacy crypto algorithms, streaming and AMBA interface
- Supported by Driver development kit, QuickSec IPsec toolkit, Linaro ODP.
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Crypto Coprocessor (Premium)
- The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC.
- Symmetric operations are offloaded very efficiently as it has a built-in scatter/gather DMA. The coprocessor can be used to accelerate/offload IPsec, VPN, TLS/SSL, disk encryption, or any custom application requiring cryptography algorithms.
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Crypto Coprocessor (Compact)
- The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC.
- Symmetric operations are offloaded very efficiently as it has a built-in scatter/gather DMA. The coprocessor can be used to accelerate/offload IPsec, VPN, TLS/SSL, disk encryption, or any custom application requiring cryptography algorithms.
