40nmULP Memory Compiler IP
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Bulk 40ULP single port SRAM Compiler - ultra low power, low power retention mode
- Uses low leakage devices and source biasing to minimize standby currents.
- Dedicated standy mode with built in source biasing for the memory array.
- Periphery and array supplies are isolated to allow power off of the perphery when in standy mode.
- .8V supply voltage
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Bulk 40ULP Single Port SRAM with low power retention mode, high speed pins on 1 side
- Ultra low power data retention. Memory instances generated by the Bulk 40 ULPgo into a deep sleep mode that retains data at minimal power consumption.
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Ultra Low Voltage Embedded SRAM - TSMC 40ULP
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
- ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
- Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
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Ultra Low Voltage Embedded SRAM - TSMC 22ULL
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
- ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
- Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
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Ultra Low Voltage Embedded SRAM - TSMC 28HPC+
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
- ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
- Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
