28nm UMC IO Pad IP
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4
IP
from 2 vendors
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4)
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USB 2.0 femtoPHY in UMC (28nm, 22nm)
- Complete mixed-signal physical layer for single-chip USB 2.0 Host, Device, and Dual Role applications Small PHY macro area: as small as 0.20 mm2
- Low power: as low as 50mW (during high-speed packet transmission)
- Advanced power management features including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support
- Supports USB 2.0 ID-pin detection and OTG Voltage Detectors
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USB 2.0 picoPHY in UMC (40nm, 28nm)
- Complete mixed-signal physical layer for single-chip USB 2.0 OTG and non-OTG applications
- Small PHY macro area
- Low power
- Advanced power management features, including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support
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DDR4 multiPHY - UMC 28HPC18
- Support for JEDEC standard DDR4, DDR3, LPDDR2, and LPDDR3 SDRAMs
- Scalable architecture that supports data rates up to DDR4-2667
- Support for DIMMs
- Delivery of product as a hardened mixed-signal macrocell component allows precise control of timing critical delay and skew paths
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12.5G Multiprotocol Serdes IP, Silicon Proven in UMC 28HPC
- A universal SERDES IP that operation from 1Gbps to 12.5 Gbps
- Compatible with PCIe/USB3/SATA base Specification
- Support 40-bit/32-bit/20-bit/16-bit parallel interface
- Support for PCIe2(5.0Gbps), USB3.0(5.0Gbps) and SATA3(6.0Gbps)