16nm SerDes IP
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45
IP
from 3 vendors
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10)
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PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
- Compatible with PCIe base Specification
- Full compatible with PIPE3.0 interface specification
- Independent channel power down control
- Implemented Receiver equalization Adaptive-CTLE to compensate insertion loss
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PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
- Compliant with PCIe 3.0 Base Specification
- Compliant with PIPE 4.3
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
- Supported physical lane width: x4
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PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
- Compliant with PCIe 4.0 Base Specification
- Compliant with PIPE 4.4
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0 GT/s
- Supported physical lane width: x4
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PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
- Compliant with PCIe 5.0 Base Specification
- Compliant with PIPE 5.1
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s, 16.0 GT/s and 32GT/s
- Supported physical lane width: x4
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TSMC CLN16FF+LL 16nm Ultra PLL - 15MHz-3000MHz
- New state-of-the-art architecture using high-speed digital and analog circuits that offers unprecedented operating ranges and extremely high performance.
- Ultra low jitter performance for the most demanding SerDes and ADC reference clocks.
- Ultra wide frequency range with multiplication factors over 250,000 to support 32KHz to 1GHz references.
- Precise frequency control with a least 26 fractional bits (at least 10 precise) for extremely high fractional-N resolution.
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TSMC CLN16FFCLL 16nm Clock Generator PLL - 800MHz-4000MHz
- Designed as a very flexible clock multiplier capable of multiplying an input clock from 1 to 4096 with very small period jitter while operating at the highest possible bandwidth.
- Delivers optimal jitter performance over all multiplication settings.
- Available with multi-phase outputs and, in some processes, with an I/O voltage regulator.
- Ideal for system clock generation, SerDes and video clock applications.