IP Catalog > 16G PCIe Gen 4 Controller

16G PCIe Gen 4 Controller IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Search (11)
Compare 11 IP from 3 vendors (1 - 10)
  • PCIe 4/3/2 SerDes PHY - Samsung 14nm
    • Duplex lane configurations of x2, x4, and x35
    • Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
    • Support for AC-coupled interfaces
    • Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
  • PCIe 4/3/2 SerDes PHY - GLOBALFOUNDRIES 12nm
    • Duplex lane configurations of x2, x4, and x35
    • Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
    • Support for AC-coupled interfaces
    • Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
  • PCIe 4/3/2 SerDes PHY - GLOBALFOUNDRIES 22nm
    • Duplex lane configurations of x2, x4, and x35
    • Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
    • Support for AC-coupled interfaces
    • Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
  • 16G Multi-Protocol SerDes (MPS) PHY - Samsung 14nm
    • Duplex lane configurations of x2, x4, and x38
    • Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
    • Support for AC-coupled interfaces
    • Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
  • 16G Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 12nm
    • Duplex lane configurations of x2, x4, and x38
    • Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
    • Support for AC-coupled interfaces
    • Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
  • 16G Ethernet SerDes PHY - Samsung 14nm
    • Duplex lane configurations of x2, x4, and x40
    • Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
    • Support for AC-coupled interfaces
    • Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
  • 16G Ethernet SerDes PHY - GLOBALFOUNDRIES 12nm
    • Duplex lane configurations of x2, x4, and x40
    • Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
    • Support for AC-coupled interfaces
    • Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
  • 16G PHY in TSMC (N7) for Automotive
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 6.0 (PAM-4), 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
    • Supports x1, x2, x4, x8, and x16 hard macro configurations
    • Lane margining at the receiver
  • 16G PHY in TSMC (28nm, 16nm, 12nm, N7, N6)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 6.0 (PAM-4), 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
    • Supports x1, x2, x4, x8, and x16 hard macro configurations
    • Lane margining at the receiver
  • 16G PHY in Samsung (14nm, 11nm)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 6.0 (PAM-4), 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
    • Supports x1, x2, x4, x8, and x16 hard macro configurations
    • Lane margining at the receiver
×
Semiconductor IP