112Gbps PAM4 SerDes IP
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112G-ELR PAM4 SerDes PHY - TSMC 5nm
- TSMC 5nm FinFET CMOS Process
- Power-optimized for ELR and LR links
- Integrated BIST capable of producing and checking PRBS
- 56-112Gbps PAM4 or 1-56Gbps NRZ data rates
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112G-XSR Pam4 for TSMC 7nm FinFET CMOS
- TSMC 7nm FinFET CMOS Process
- 112G PAM4 interface compatible to LR and VSR
- Eight-lane compact footprint for high-density designs
- Integrated BIST capable of producing and checking PRBS
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1-112Gbps Medium Reach (MR) and Very Short Reach (VSR) SerDes
- High speed performance
- Low power architecture
- Sub-sampling clock multiplier
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Complete 1.6T Ultra Ethernet IP Solution
- Ethernet MAC, PCS and PHY to complete a full Ultra Ethernet interface stack
- Supports evolving IEEE 802.3 and OIF-224G electrical standards
- Provides support for 4 x 400G, 2 x 800G, and 1.6T Ethernet rates using 112Gbps and 224Gbps SerDes
- Meets performance criteria for chip-to-chip, chip-to-module, and long reach copper/backplane interconnects
