112Gbps PAM4 SerDes IP
Filter
Compare
9
IP
from 4 vendors
(1
-
9)
-
112G-ELR PAM4 SerDes PHY
- Interoperability
- Maximize beach front bandwidth
- Layout flexibility
-
112G-ELR PAM4 SerDes PHY - TSMC 7nm
- TSMC 7nm/6nm FinFET CMOS Process
- Power-optimized for ELR LR and MR links
- Fully autonomous startup and adaptation without requiring ASIC intervention
- 112/56Gbps PAM4 or 56/28/10Gbps NRZ data rates
-
112G-ELR PAM4 SerDes PHY - TSMC 5nm
- TSMC 5nm FinFET CMOS Process
- Power-optimized for ELR and LR links
- Integrated BIST capable of producing and checking PRBS
- 56-112Gbps PAM4 or 1-56Gbps NRZ data rates
-
112G-XSR Pam4 for TSMC 7nm FinFET CMOS
- TSMC 7nm FinFET CMOS Process
- 112G PAM4 interface compatible to LR and VSR
- Eight-lane compact footprint for high-density designs
- Integrated BIST capable of producing and checking PRBS
-
112Gbps Serdes USR & XSR
- BIST generator and checker;
- Support data polarity inversion;
- TX/RX status control;
-
112Gbps VSR to extended LR SerDes IP on TSMC N5/N4
- TSMC N5/N4 process
- Excellent performance for VSR to extended LR channels from 1G NRZ to 100Gbps PAM4 data rates
-
112Gbps VSR to extended LR SerDes IP on TSMC N7/N6
- Excellent performance for VSR to extended LR channels from 1G NRZ to 100Gbps PAM4 data rates
-
112Gbps VSR to extended LR SerDes IP on TSMC 16/12nm
- TSMC 16/12nm process
- Excellent performance for VSR to extended LR channels from 1G NRZ to 100Gbps PAM4 data rates
- Ultra low power
- Area & Power: Please contact us
-
1-112Gbps Medium Reach (MR) and Very Short Reach (VSR) SerDes
- High speed performance
- Low power architecture
- Sub-sampling clock multiplier
