10G Full TCP Accelerator IP
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4
IP
from 2 vendors
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10G TCP Endpoint
- FullTCP/IP stackin FPGA logic
- Ultra-low latency
- Parameters
- Streaming Interfaces with in-order data
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40G/25G/10G/1G UDP/IP + MAC
- Management of layers 1, 2, 3 and 4 (OSI Model), compliant with
- Layers 1 and 2: Physical and Data Link
- PHY Interface
- Raw MAC Stream Interface (access to MAC in promiscuous/transparent mode)
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40G/25G/10G/1G TCP/IP + MAC
- Management of layers 1, 2, 3 and 4 (OSI Model), compliant with
- Layers 1 and 2: Physical and Data Link
- PHY Interface
- Raw MAC Stream Interface (access to MAC in promiscuous/transparent mode)
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10G Ultra-low latency TCP/IP + MAC + PCS IP core for FPGAs
- Best-in-class ultra-low latency from wire to user’s logic.
- 10G Ethernet connectivity. Maximum bandwidth delivered.
