Warping Engine IP block for image transformation, HUDs and fish-eye correction

Overview

TES Warping Engine is a specialized IP core for arbitrary high-performance re-mapping of bitmaps from memory-to-memory or memory-to-stream. Applications are for example pre-warping for projection on head-up displays or fisheye-correction of camera images.

The IP core adapts to different bus interfaces like AMBA APB and AHB/AXI as well as the Altera Avalon bus interface at different bus width (e.g. 32, 64, 128 bits).

Key Features

Arbitrary mapping
- Based on a output->input look-up table per pixel
- Highly-efficient compression algorithm for the mapping LUT
High-quality bilinear filtering
- 16 x 16 subpixel positions
High performance
- Sophisticated caching mechanism proven in TES rendering engines
Flexible Color Formats
- Input and output formats selectable at run-time
- Available formats fully configurable at synthesis time, e.g.:
- ARGB8888
- ARGB4444
- ARGB1555
- RGB565
- RGBA8888
- RGBA4444
- RGBA5551
- 8 bit grayscale
- etc.
Output to Memory or as AXI stream

Benefits

Highly configurable Warping Engine supporting cropping as well as scaling.
Warping Look-Up-Table with TES adaptive compession technology for optimal trade of between warping error and memory bandwidth consumption.
Powerful tooling for generation of Warping Look-Up-Tables
Easy SoC Integration
Low resource consumption

Applications

Camera fish-eye correction
Image transformation, cropping and scaling
Head-Up-Displays
Projectors

Deliverables

Warping IP Block,
Simple basic software driver written in ANSI-C to configure and control the warping engine
Example Application
Powerful Tools for generation and compression of Warping Look-Up-Table

Technical Specifications

Maturity

FPGA proven

Availability

now

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