UDP Network Interface with Ethernet MAC for the M8051W and M8051EW

Overview

Key Features

• Simple IP datagram interface providing transport- level exchange of data over IP networks
• Compatible with the RFC768 UDP specification
• Includes a simple ARP protocol handler, suitable for point-to-point connections to switches
• An RFC894 compatible Ethernet MAC
• Integral MDIO controller interfaces to external PHY devices using a 1 gigabit RGMII interface
• Programmable MAC, IP and port addresses
• DMA controller automates data transfers between network and host data memory, interrupt and SFR buses with no additional glue logic required
• Integral transmit and receive data FIFOs minimise the processor overhead required to service the link
• Supports DMA, interrupt-driven and polled data transfers
• Asynchronous data FIFOs enable host clock to operate asynchronously to the PHY clock
• Optional clock prescaler minimises power consumption while active
• Rests in power saving mode when the interface is not enabled
• Wake up on MAC address, or IP address match, can be used to cold start a M8051W and M8051EW microcontroller, in addition to interrupt driven wake ups
• Binds tightly to M8051W and M8051EW external data buses

Deliverables

• VHDL 93 and Verilog 2001 RTL source code
• VHDL and Verilog functional demonstration testbench
• Demonstration assembler code
• Simulation scripts for Modelsim and Cadence
• Synopsys synthesis compile scripts and SDC timing constraint files
• Example Mentor DFT and ATPG scripts
• Example netlist implementation with SDF files
• Detailed product specification and a user guide containing implementation notes

Technical Specifications