TSMC CLN40FLOD 40nm Multi Phase DLL - 150MHz-750MHz
Overview
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock. It delivers optimal jitter performance over a wide frequency range. The analog delay-line architecture used in our DLL design is internally isolated from supply noise for very low output jitter. The analog delay line also provides duty cyle correction.
Key Features
- Designed for high-speed interface applications.
- Generates precise multi-phase clocks directly from the reference clock.
- Delivers optimal jitter performance over a wide frequency range.
Deliverables
- GDSII (100% DRC and LVS clean)- LVS Spice netlist- Verilog model- Synopsys synthesis model- LEF for clock generator PLL- User Guidelines including:
- integration guidelines,
- layout guidelines,
- testability guidelines,
- packaging guidelines,
- board-level guidelines
Technical Specifications
Foundry, Node
TSMC CLN40FLOD
TSMC
Pre-Silicon:
40nm
G
,
40nm
LP
Related IPs
- TSMC CLN40ULPOD 40nm Multi Phase DLL - 150MHz-750MHz
- TSMC CLN40FL 40nm Multi Phase DLL - 150MHz-750MHz
- TSMC CLN40FLOD 40nm Multi Phase DLL - 300MHz-1500MHz
- TSMC CLN40FLOD 40nm Multi Phase DLL - 75MHz-375MHz
- UMC L28EHV 28nm Multi Phase DLL - 150MHz-750MHz
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)