Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm SP process
Overview
UMC 55nm SP/RVT Logic process 7-Track POWERSLASH Cell Library.
Technical Specifications
Foundry, Node
UMC 55nm SP
UMC
Pre-Silicon:
55nm
Related IPs
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- Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm LP process
- Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 55nm SP process
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