SPI Slave To SOC Bridge IIP

Overview

SPI Slave To SOC Bridge interface provides full support for the two-wire SPI synchronous serial interface, compatible with SPI version Block Guide 4.01 standard. Through its SPI compatibility, it provides a simple interface to a wide range of low-cost devices. SPI Slave To SOC Bridge IIP is proven in FPGA environment.The host interface of the SPI can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.Basically SPI SOC Bridge IP is used to convert SPI into SOC bus protocol.

SPI Slave To SOC Bridge IIP is supported natively in Verilog and VHDL

Key Features

Compliant with the SPI Block Guide 4.01 standard.
Full SPI Slave functionality.
Converts SPI Transactions into SOC write or read access.
Allows external devices to access the internal SOC Bus
Useful for updating device software from and external device
Useful for reading internal memory mapped registers and memory
Supports Mailbox Read/Write functionality
Supports SOC Master Read/ Write capability
Supports SOC Slave
Supports monitoring of erroneous SOC transfers and reports error to the system
Supports Single/Dual/Qual/Octal SPI Data line.
Support power mode commands also.
Supports flexible transfer format to work with slower interfaces
Supports address width of 8,16,24 and 32 bits
Supports following frames for SPI

Sleep Frame
Wakeup Frame
Write Frame
Read Frame
Extended Register Write Frame
Extended Register Read Frame
Extended Register Write Long Frame
Extended Register Read Long Frame
Extended Register Write Long Long Frame
Extended Register Read Long Long Frame

Support single and burst transfer mode for SPI
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple interface allows easy connection to microprocessor/microcontroller devices

Benefits

Single Site license option is provided to companies designing in a single site.
Multi Sites license option is provided to companies designing in multiple sites.
Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Block Diagram

Deliverables

The SPI Slave To SOC Bridge interface is available in Source and netlist products.
The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
Easy to use Verilog Test Environment with Verilog Testcases
Lint, CDC, Synthesis, Simulation Scripts with waiver files
IP-XACT RDL generated address map
Firmware code and Linux driver package
Documentation contains User's Guide and Release notes.

Technical Specifications

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