RAMA IP
Overview
Thread Synthesis and Reordering attachment IP for use with random access masters to HBM IP
Key Features
- Thread Synthesis, allows instructions to complete out of order, relieving congestion in the HBM switch
- Coalesces sparse read data
- Acknowledges instructions and returns read data in the order in which they were received
- Supports the maximum transaction size, 512B
- Ideal for masters accessing more than one HBM Pseudo Channel
Technical Specifications
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