MIPI M-PHY Compliant (HS-G2) IP

Overview

The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY. The IP can be used as a physical layer for many applications, including interfaces for display, camera, audio, video, memory, power management and Baseband to RFIC.
It supports the following standards: DigRF v4, CSI-3, DSI-2, Uniport-M (UniPro1.5) and JC-64.1 UFS.
By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained.
Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates.

Key Features

Complies with MIPI Standard for M-PHY, Draft Specification v0.90.
Dual-simplex point-to-point interface with ultra low voltage differential signaling
Slew-rate control for EMI reduction
Supports all HS modes (GEAR 1-2)
Supports all Type-I LS modes (GEAR 0-7)
Supports Type I & II LS mode
1-3Gbps data rate in HS mode
0.01-576Mbps data rate in LS mode
Suitable for copper and optical media
Modular design to allow for all possible configurations
Low power dissipation
Uses "Legorithmic" approach to allow for all possible configurations

Block Diagram

Applications

Mobile
Displays
Cameras/Sensors
IoT
VR/AR/MR
Consumer electronics
Automotive
Storage

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Maturity

Silicon Proven

Availability

Now

SMIC

Silicon Proven: 130nm G

TSMC

Silicon Proven: 28nm HPL , 28nm HPM , 65nm LP

UMC

Silicon Proven: 40nm LP

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