JTAG (IEEE 1149.1/1149.6) Verification IP

Overview

JTAG (IEEE 1149.1/1149.6) Verification IP provides a smart way to verify the JTAG (IEEE 1149.1/1149.6) component of a SOC or a ASIC. The SmartDV's JTAG Verification IP works in a highly randomized manner to generate wide range of scenarios for effective verification of DUT.

JTAG Verification IP includes an extensive test suite covering most of the possible scenarios and detection of protocol violation using a effective protocol-checker.

JTAG (IEEE 1149.1/1149.6) Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

JTAG (IEEE 1149.1/1149.6) Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Follows JTAG basic specification as defined in JTAG Specification 3.
Supports Jtag protocol standard IEEE 1149.1 and IEEE 1149.6.
Supports all the JTAG tap instructions.
Supports programmable clock frequency of operation.
Checks for following
- State based rules
- Active Command rules
- Read/Write to Instruction and Data register rules
Supports Instruction register and Data register of size upto 64 bits.
Proficiency to extend with user defined instructions and registers.
Proficiency to extend with user defined functional coverage points.
Has ability to read BSDL file and
- Automatically generate testvectors to test all BSDL cell types
- Automatically generate functional coverage points to check if all possible BSDL cell testing is complete
- Automatically generate SVA assertions properties
Supports constraints randomization.
Status counters for various events on bus.
Supports callbacks for user to define custom instruction decoder.
Supports callbacks for user to get callback on each state of TAP controller.
Support all types of timing and protocol violation detection.
Functional safety features (B: No certification, with safety features, in line with the development process)
Notifies the testbench of significant events such as transactions, warnings, timing and Protocol violations.
Functional coverage for checking all possible stimulus checking.

Benefits

Faster testbench development and more complete verification of JTAG designs.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the JTAG IEEE 1149.1 testcases.
Examples showing how to connect various components, and usage of BFM and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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