JPEG XS compression IP core for HD - Max fps: 60 - Color sampling: 4:2:2 / 4:0:0

Overview

intoPIX has developed various optimized TicoXS architectures running a different pixel per clock to target a wide range of resolutions and a wide range of FPGA devices & ASIC technology nodes.

TicoXS is a revolutionary compression technology, standardized as JPEG XS, extremely tiny in FPGA & ASIC. It fits into the smallest AMD (Xilinx) or Intel (Altera) devices, it is robust for real-time operation with no latency. It offers a very low gate count & SRAM consumption in ASICs.

Key Features

Image/Video Features
- Color space: Any (RGB, YCbCr, YUV, XYZ)
- Color Sampling: 4:2:2, 4:4:4, 4:0:0 (monochrome, Alpha); 4:2:0* and 4:2:2:4*
- Bit Depth: 8, 10, 12, 14, 16
- Interlaced & Progressive frame
- Image/Video Resolutions: Any (SD, HD, 2K, 4K, 5K, 8K, 10K,...)
- HDR ( & SDR ) support
- Frame Rates: Regular and High Frame Rates (depending on intoPIX IP-core configuration & targeted device).
  - For Real-time video and High speed video (up to more than 1000 fps)
TicoXS Compression (Latency, Quality, Rate Control)
- (Sub) intra-frame - Few of video lines buffering only
- JPEG XS compliant (ISO/IEC 21122-1) , including coding profiles such as High444.12, MLS.12 , etc.
- Real-time operation guaranteed (no overflow or underflow)
- Fixed latency - Only few lines of pixels (number of lines depends on the profile)
- Adjustable compression rate for lossy / visually lossless (down to 1.5 bpp**) / near-lossless / math. lossless
- Full transparency to uncompressed down to 3 bits per pixel (bpp)
- CBR (constant bit rate) operation - Adjustable down to 36:1 (1bpp)
- Optional Add-On: Embedded x1 (1/4) and x2 (1/16) Downscaler: The decoder cores can extract proxy / low resolution during the decoding
- Optional Add-On: New Master + Proxy1K Encoding: From the same source, the encoder cores simultaneously generate a low resolution / low bitrate proxy Stream on top of the full resolution / high quality Master Stream. The Proxy1K stream is adjustable in bitrate and CBR and has the same 'line-based latency.
- Optional intoPIX "Flawless Imaging" - new JPEG XS TDC profile for KVM, AVoIP, IPMX, PC applications. See TicoXS FIP solutions
FPGA/ASIC Implementation
- Low-cost implementation in any FPGAs: very low FPGA logic and internal RAM usage (No external DDR required)
  - Running in the smallest AMD (Xilinx) Spartan-6, Spartan-7 Artix-7, Kintex-7 and Ultrascale , Ultrascale Plus, Zynq, Versal, Adaptive SOC FPGA
  - Running in the smallest Altera (Intel) Cyclone V, Arria V, Stratix V, Cyclone 10, Arria 10, Stratix 10, Agilex FPGA
  - Running in the smallest Lattice Lattice Certus Pro and Avant FPGA
- Low Gate Area (low gate count / low memory) for ASIC
- Encoder and decoder have approximately the same complexity
- IP Core size, performance, video resolution & max frame per second - customizable per application*
- Various pixel per clock architectures

Benefits

Max res: 1920x1080
Max fps: 60
Color sampling: 4:2:2 / 4:0:0
Bit depth: 8, 10, 12
Minimum frequency (internal core clock): 45 MHz

Applications

Technical Specifications

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