Perceptia’s DeepSub™ pPLL08F is a family of high performance RF frequency synthesizer PLLs featuring industry leading jitter (sub-300fs), phase noise and compact area suitable for RF applications, including 5G and WiFi at frequencies up to 8GHz. It is suitable for use as an LO and/or clocking ADCs/DACs with demanding SNR requirements.
Perceptia’s second generation pPLL08F family is available on technologies from 5nm to 40nm and across multiple foundry partners. We are continually expanding the range of technologies where it is silicon proven and can quickly port it to other technologies or foundries upon request.
pPLL08 uses a LC tank DCO to achieve the performance demands of critical RF systems. It is low power (< 3 mW in GF 22FDX) and is extremely compact (< 0.05 sq mm). The all digital architecture minimises interference from other circuits on the same die, making it capable of supporting SNDR better than 60dB.
pPLL08 integrates easily into any SoC design and includes all the views and models required by back end flows.
The pPLL08F is built using Perceptia’s second generation all digital PLL technology. This robust technology delivers identical performance across many processes, regardless of PVT conditions. It consumes a fraction of the area of an analog PLL whilst maintaining comparable performance.
pPLL08F can be used as an integer-N PLL or as a fractional-N PLL. The fractional-N mode provides a high flexibility to choose the best combination of input and output clock frequencies at the system level.
Perceptia further provides integration support and offers customization and migration services.
High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
Overview
Key Features
- Ultra-low jitter, less than 300fs RMS integrated between 12kHz to 20MHz.
- Suitable for many RF applications, including LO, clocks for, ADC, DAC, high-speed PHY
- Small die area (< 0.05 sq mm), using a LC tank oscillator
- Output frequency can be from 1 to 2047 times the input reference, up to 8GHz
- Reference clock from 5MHz to 1GHz
- Second-generation digital PLL architecture, providing integer and 24 bit fractional multiplication
- Primary PLL output running at the main DCO frequency for lowest noise clocking
- Two further PLL outputs via separate postscalers
- Post-scalers programmable from 1 to 2,040
- Lock-detect output
- PLL output duty cycle better than 49 / 51%
- Highly testable using industry standard flows
- ATPG vectors provided
- Specification of functional tests to supplement ATPG testing
Benefits
- Fractional Multiplication with frequencies up to 8GHz
- Extremely low jitter (< 300fs RMS)
- Small size (< 0.05 sq mm)
- Low Power (< 3 mW in GlobalFoundries 22FDX)
- Support for many wireless standards including 5G and WiFi
- Easy integration
Block Diagram
Applications
- RF LO
- Clock for RF ADC/DAC
- 5G and LTE radio (3GPP)
- WiFi Radio (802.11ax)
- SerDes
- Optical transceiver
Deliverables
- Datasheet
- Detailed Verilog behavioral model
- Timing models
- LEF5.6 abstract for floor planning/chip assembly
- Integration Guide
- DFT Guide
- Integration support
- Characterization report
- GDSII layout macrocell
- CDL netlist for LVS
- DRC, LVS and SI verification reports
- Netlist model with accompanying documentation – allowing integration of the module in scan chains
Technical Specifications
Foundry, Node
From 5nm to 65nm
Maturity
In production
Availability
Now
GLOBALFOUNDRIES
Pre-Silicon:
12nm
,
14nm
,
14nm
LPE
,
14nm
LPP
,
20nm
LPM
,
28nm
,
28nm
FDSOI
,
28nm
HPP
,
28nm
LPH
,
28nm
SLP
,
32nm
,
40nm
LP
,
55nm
,
55nm
LPX
,
65nm
,
65nm
LP
,
65nm
LPe
SMIC
Pre-Silicon:
14nm
,
28nm
,
28nm
HK
,
28nm
HKC+
,
28nm
PS
,
40nm
LL
,
55nm
G
,
55nm
LL
,
65nm
LL
Samsung
Pre-Silicon:
7nm
,
10nm
,
28nm
FDS
,
28nm
LPH
,
28nm
LPP
,
32nm
LP
,
45nm
LP
,
65nm
LP
TSMC
Pre-Silicon:
5nm
,
7nm
,
10nm
,
12nm
,
16nm
,
20nm
,
22nm
,
28nm
,
28nm
HP
,
28nm
HPC
,
28nm
HPCP
,
28nm
HPL
,
28nm
HPM
,
28nm
LP
,
40nm
G
,
40nm
LP
,
45nm
GS
,
45nm
LP
,
55nm
FL
,
55nm
G
,
55nm
GP
,
55nm
LP
,
55nm
NF
,
55nm
ULP
,
55nm
ULPEF
,
55nm
UP
,
65nm
G
,
65nm
GP
,
65nm
LP
UMC
Pre-Silicon:
14nm
,
28nm
,
28nm
HLP
,
28nm
HPC
,
28nm
HPM
,
28nm
LP
,
55nm
,
65nm
LL
,
65nm
LP
,
65nm
SP
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- High Performance Fractional-N RF Frequency Synthesizer PLL in Samsung 8LPP for 5G, WiFi, etc
- High Performance Fractional-N RF Frequency Synthesizer PLL in Samsung 14LPP for 5G, WiFi, etc
- High Performance Fractional-N RF Frequency Synthesizer PLL in UMC 40LP
- Fractional-N Frequency Synthesizer PLL