Differential Signal Receiver on TSMC CLN5A

Overview

The Differential Signal Receiver macro is a receiver including AC input coupling, and addresses a large portfolio of applications. The Receiver is designed for digital logic processes and use robust design techniques to work in noisy SoC environments, ranging from high speed communication to low power consumer applications.

The Receiver macro is implemented in Analog Bits’ proprietary architecture that uses core and IO devices at core voltage only. In order to minimize noise coupling and maximize ease of use, the Receiver incorporates signal ESD structures and a power supply ESD structure.

Key Features

  • Differential IO clock receiver
  • Single-ended output to chip core
  • AC coupled input structure to allow a wide range of input common mode voltages
  • Wide Ranges of input frequencies up to 2000MHz for diverse clocking needs
  • Implemented with Analog Bits’ proprietary architecture
  • Low power consumption
  • Spread Spectrum tracking capability
  • Requires no additional on-chip components or band-gaps, minimizing power consumption
  • Designed for AEC-Q100 Automotive Grade 2 operation.

Technical Specifications

Foundry, Node
TSMC CLN5A
TSMC
Pre-Silicon: 5nm
×
Semiconductor IP