DDR5 Assertion IP

Overview

Key Features

• Specification Compliance
  • Supports DDR5 memory devices from all leading vendors.
  • Supports 100% of DDR5 protocol standard JESD79-5 & JESD79-5 Rev1.40 (Draft).
  • Supports all the DDR5 commands as per the specs.
  • Supports up to 64GB device density.
  • Supports the following devices.
  • X4
  • X8
  • X16
  • Supports all speed grades as per specification.
  • Supports Write Pattern command.
  • Supports Auto precharge for Write, Read and Write pattern command.
  • Supports CA, CS and Read Preamble training modes.
  • Supports MIR and CAI operations.
  • Supports Read training pattern.
  • Supports Write leveling training mode.
  • Supports Programmable Write latency and Read latency.
  • Supports Programmable Preamble, Postamble and Interamble.
  • Supports Programmable burst lengths: 8, 16, 32.
  • Supports Sequential burst type and Burst order.
  • Supports 2N mode.
  • Supports all mode register programming.
  • Supports Write data mask.
  • Supports CRC for Write, Read and MRR operations.
  • Supports DLL features.
  • Checks for following
  • Check-points include power up, Initialization and power off rules
  • State based rules, Active Command rules
  • Read/Write Command rules etc.,
  • All timing violations
  • Supports Self Refresh and Power down operation.
  • Supports Partial Array Self Refresh (PASR).
  • Supports Self Refresh Entry with frequency change (SREF)
  • Supports Refresh modes and Global refresh counter.
  • Supports Refresh management all command.
  • Supports Adaptive Refresh Management (ARFM).
  • Supports Directed Refresh Management (DRFM).
  • Supports Refresh management same bank command.
  • Supports for temperature compensated refresh reporting
  • Supports Maximum power saving mode.
  • Supports Post Package Repair (PPR).
  • Supports hard Post Package Repair (hPPR)
  • Supports soft Post Package Repair (sPPR)
  • Supports Memory Built-In Self Test-Post Package Repair (mPPR)
  • Supports Loop back concepts.
  • Supports Target row refresh
  • Supports per DRAM Addressability.
  • Supports Precharge command modes.
  • Supports Multipurpose Command (MPC).
  • Supports VrefCA command.
  • Supports VrefCS command.
  • Supports Vref CA, Vref CS and Vref DQ training.
  • Supports ZQ calibration
  • Supports input clock stop and frequency change.
  • Supports On-Die Termination (ODT).
  • Supports Connectivity Test (CT) mode.
  • Supports all timing delay ranges in one model: min, typical and max.
  • Protocol checker fully compliant with DDR5 Specifications JESD79-5 & JESD79-5 Rev1.40 (Draft).
  • Constantly monitors DDR5 behavior during simulation.
• Assertion IP features
  • AIP includes:
  • System Verilog assertions.
  • System Verilog assumptions.
  • System Verilog cover properties.
  • Synthesizable Verilog Auxiliary code.
  • Supports Control mode, Model mode, Monitor mode and Constraint mode.
  • Supports Simulation mode (stimulus from SmartDV DDR5 VIP) and Formal mode (stimulus from Formal tool).
  • Rich set of parameters to configure DDR5 AIP functionality.

Benefits

• Runs in every major formal and simulation environment.

Block Diagram

Deliverables

• Detailed documentation of Assertion IP usage.
• Documentation also contains User's Guide and Release notes.

Technical Specifications