VeriSilicon CSMC 0.18um High-Speed Synchronous Memory Compiler optimized for CSMC TECHNOLOGIES CORPORATION Fab2 0.18um MS/RF process can flexibly generate memory blocks via a friendly GUI or shell commands.
The compiler supports a comprehensive range of word and bit lengths. While satisfying speed and power requirements, it has been optimized for area efficiency.
VeriSilicon CSMC Synchronous Memory Compiler uses four layers within the blocks and supports metal 4, 5 or 6 as the top metal. Dummy bit cells are synthesized with the intention to enhance reliability
CSMC 0.18um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler
Overview
Key Features
- High Density
- High Speed
- Size Sensitive Self-Time Delay for Fast Access
- Automatic Power Down
- Tri-State Output(SRAM only)
- Write Mask Function(SRAM & Register File)
Technical Specifications
Foundry, Node
CSMC 0.18um
Maturity
Silicon proven
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