6 track Ultra High Density standard cell library at TSMC 90 nm with dual voltage capability
Overview
TSMC 90 uLL, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest alternative to flip-flops).
Key Features
- Ultra High Density
- Up to 15% smaller area after P&R compared to standard 7-Track library
- Pulsed latches as Spinner Cells instead of SCAN D-flip-flops: for 30% gain in density at cell level
- Metal layer 2 available for routing as only Metal 1 used for cell design
- 6-Track cells for optimal area reduction
- Configuration
- uLL MOS versions for the lowest dynamic power and leakage power
- Power reduction features
- 30% less consumption of dynamic power with 6 rather than usual 7 Tracks at 1.2 V+/-10%
- Low Voltage Capability for additional power savings when operating down to 1.0 V +/-10%
- Easy implementation
- Pulse generation automated by the script for Insert pulse generation
- Spinner cell design minimizing hold time violations
- Optimal Design for Yield
- Design methodology ensuring High-Yield circuits despite Mismatch
Technical Specifications
Maturity
Pre-silicon
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