3GPP LTE 3GPP2 1xEV-DO Turbo Decoder with Ping Pong Input and Output Memories

Overview

Key Features

• Turbo Decoder
• 8 state 3GPP LTE and 3GPP2 1xEV-DO Release B compatible
• Rate 1/2, 1/3, 1/4 or 1/5
• 40 to 6144 (3GPP LTE) or 17 to 20730 (3GPP2) bit interleaver
• Includes ping-pong input and output memories
• Optional external interleaver parameters for 3GPP LTE and programmable row coefficients for 3GPP2 interleaver
• Up to 107 MHz internal clock
• Up to 10.2 Mbit/s with 5 decoder iterations
• 6-bit signed magnitude input data
• Optional log-MAP or max-log-MAP constituent decoder algorithms
• Up to 128 iterations in 1/2 iteration steps
• Optional power efficient early stopping
• Optional extrinsic information scaling and limiting
• 16 or 24 bit CRC check
• Implement one or two different standards from the one core
• Free simulation software
• Available as EDIF core and VHDL simulation core for Xilinx Virtex-II Pro, Spartan-3, Virtex-4 and Virtex-5 FPGAs under SignOnce IP License. Actel, Altera and Lattice FPGA cores available on request.
• Available as VHDL core for ASICs
• Low cost university license also available

Deliverables

• All licenses
• EDIF core
• VHDL simulation core
• Test vector generation software
• VHDL ASIC License
• VHDL ASIC core
• C++ bit/cycle exact simulation model

Technical Specifications