3.3V to 0.3V and VCCK-0.3V / 10mA voltage source for N/P well forward body bias, Linear Regulator, UMC 55nm uLP/RVT Low-K Logic Process
Overview
3.3V to 0.3V and VCCK-0.3V / 10mA voltage source for N/P well forward body bias, Linear Regulator, UMC 55nm uLP/RVT Low-K Logic Process
Technical Specifications
Foundry, Node
UMC 55nm Logic/Mixed_Mode uLP
UMC
Pre-Silicon:
55nm
Related IPs
- On-Chip IO to Core Voltage Buck Regulator on UMC 55nm ULP
- Linear Voltage Regulator - High Input Voltage (30V), Output Load up to 5mA
- UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell.
- UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
- UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias
- UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell