ITCADC400 is a high-speed ADC with a mixed analog-digital design. The main technology is a multi-bit quantized modulator using pipeline architecture and digital correction technology. The decimation filter is used to down-sample and increase the number of bits to improve the resolution.
The innovative architecture achieves excellent dynamic performance and is insensitive to clock jitter, which allows greater choice of devices and reduces the difficulty of future ASIC design, so it can be used for high-speed ADCs.
The innovative design allows each stage in the modulator to achieve multi-bit quantization, At the same time,it overcomes the non-linearity problem caused by the DAC for feedback comparison.
16 bit resolution 400MSPS ADC prototype
Overview
Key Features
- Input analogue signal:single 0-5V
- Sampling rate:400MSPS
- Output bit:16
- Signal to Noise Ratio(SNR):84.5dB
- Spurious-Free Dynamic Range(SFDR): 93dB
- Multistage down-sampling filter
- Differential system clock
- Supports standard SPI interface
- Channel:1
Applications
- Industrial control, chemical processes, medical image, wireless infrastructure, broadband RF signal processing, software radio, radar, military communications,electronic test and measurement, autonomous driving and automotive radar.
Deliverables
- license and prototype