IP Catalog > Broadcast IP > Arithmetic Mathematic IP > Format Conversion IP

Format Conversion IP

Welcome to the ultimate Format Conversion IP hub! Explore our vast directory of Format Conversion IP
All offers in Format Conversion IP
Filter
Filter
Search (5)
Compare 5 Format Conversion IP from 4 vendors (1 - 5)
  • Additive White Gaussian Noise Generator
    • High precision AWGN Channel emulator.
    • Programmable Pseudo Random Generator(LFSR).
    • Programmable number of output bits.
    Block Diagram -- Additive White Gaussian Noise Generator
  • Color Camera Sensor Bayer Decoder
    • Converts Bayer image into the RGB image
    • Supports all Bayer pattern combinations
    • Optional built-in LVDS receiver compatible with the Micron MT9V022 automotive sensor
    • Unlimited vertical pixel resolution
  • Single precision, IEEE 754, integer to floating point conversion
    • Single-precision (32-bit) integer to floating point conversion.
    • IEEE 754 compliant.
    • Support for signed and unsigned integers.
    • Status flags indicating invalid.
  • Single precision, IEEE 754, floating point to integer conversion
    • Single-precision (32-bit) floating point to integer conversion.
    • IEEE 754 compliant.
    • Support for signed and unsigned integers.
    • Full support for infinities, NaNs and denormals.
  • Floating Point Megafunctions
    • Floating-point computation performance is typically a balanced combination of the frequency at which the operators run and the pipeline latency of the operator hardware. This product yields a measure of GFlop performance metric. When designing for maximum GFlop performance in an FPGA, the total number of operators that can be placed in an FPGA is vital. As such, you can parameterize the Altera floating-point megafunctions in many different ways to fine-tune GFlop performance (or, similarly, for other key metrics such as power and area) to meet the application-specific requirements. The configurable features include:
×
Semiconductor IP