Coordinates Conversion IP

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Compare 8 Coordinates Conversion IP from 4 vendors (1 - 8)
  • Additive White Gaussian Noise Generator
    • High precision AWGN Channel emulator.
    • Programmable Pseudo Random Generator(LFSR).
    • Programmable number of output bits.
    Block Diagram -- Additive White Gaussian Noise Generator
  • Arctan Function
    • Function y = atan(x)
    • Input range between 0 and 1
    • Output range between 0 and Pi/4 radians
    • Uses a quadratic polynomial with dynamic coefficients
    Block Diagram -- Arctan Function
  • 4-Quadrant Arctan Function
    • Function φ = atan2(y,x)
    • Inputs as 12-bit signed
    • Output as 19-bit signed
    • Output range between -Pi and Pi radians
    Block Diagram -- 4-Quadrant Arctan Function
  • Cosine Function
    • Function y = cos(x)
    • Input range between 0 and Pi/2 radians
    • Output range between 0 and 1
    • Uses quadratic polynomial with dynamic coefficients
    Block Diagram -- Cosine Function
  • SinCos Function
    • Combined function y = sin(x), y = cos(x)
    • Input range between -Pi and Pi radians
    • Output range between -1 and 1
    • Input values as 18-bit signed
    Block Diagram -- SinCos Function
  • Sine Function
    • Function y = sin(x)
    • Input range between 0 and Pi/2 radians
    • Output range between 0 and 1
    • Uses a quadratic polynomial with dynamic coefficients
    Block Diagram -- Sine Function
  • Floating Point Megafunctions
    • Floating-point computation performance is typically a balanced combination of the frequency at which the operators run and the pipeline latency of the operator hardware. This product yields a measure of GFlop performance metric. When designing for maximum GFlop performance in an FPGA, the total number of operators that can be placed in an FPGA is vital. As such, you can parameterize the Altera floating-point megafunctions in many different ways to fine-tune GFlop performance (or, similarly, for other key metrics such as power and area) to meet the application-specific requirements. The configurable features include:
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Semiconductor IP