The ARINC 708A Verification IP provides an effective & efficient way to verify the Avionics components of an IP or SoC. The VIP is fully compliant with ARINC 708A Specification version 1.0. The VIP is lightweight with easy plug-and-play components so that there is no hit on the design cycle time.
ARINC 708A Verification IP
Overview
Key Features
- Available in Verilog, System Verilog, and UVM.
- Control Word information can be user-configurable / Random. (Protected By parity).
- Data word header will be according to the 270 271 label Frame received from Control Word.
- Support for Hazards, Faults, and Errors.
- Error response types supported.
- Supports different memory update Mode Configurations.
- Supports a wide variety of error injection scenarios.
- Supports continuous or non-continuous transactions.
- Callbacks in Master for various events.
- Control Word is transmitted using ARINC 429 Protocol while Data Word using ARINC 708 / 708A.
- Control Words Support 270, 271 Labels Frame Format.
- Data Words Supports Label 055 Octal
Block Diagram
Technical Specifications
Related IPs
- 10G/2.5G/1G Multi-Speed Ethernet Controller IP for Automotive Applications
- Ethernet PCS IP - Integrates MAC IP to a broad range of PHY and SerDes IP
- Fast Access Controller – a plug-and-play IP solution for fast embedded Flash Programming and Memory Testing
- USB 2.0 On-The-Go IP Core, Compliance Certified
- PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
- Reed Solomon Decoder IP Core