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FFT IP

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Search (35)
Compare 35 FFT IP from 13 vendors (1 - 10)
  • Fully Configurable Radix 2 FFT/IFFT Processor
    • Radix-2 Fast Fourier Transform processor IP Core.
    • Same IP core may be used to compute both FFT and IFFT transforms without any complexity overhead.
    • Highly parameterizable/scalable design using generic I/O fixed point precision and generic internal calculations precision.
    • Bit true Matlab script model is provided to aid core fixed point precision configuration for any target application.
    Block Diagram -- Fully Configurable Radix 2 FFT/IFFT Processor
  • MIMO Radar Co-processor Engine
    • Low latency, low power and compact
    • Gives ECU headroom for track-to-object recognition and make safety decisions
    Block Diagram -- MIMO Radar Co-processor Engine
  • 32-512 Point Streaming FFT
    • Supports 32/64/128/256/512-point complex FFT and IFFT and can switch dynamically
    • Inputs and outputs data in the natural order
    • Throughput of 1 sample (In-phase I + quadrature Q) per 4 clocks; no-gap processing of the input data
    • Parameterized bit width.
    Block Diagram -- 32-512 Point Streaming FFT
  • ASIP-2
    • Platform to design Application Specific Instruction Set Processors (ASIPs).
    • Ideal for supporting multi-standard systems.
    • Supports a wide range of complex DSP functions.
    • The ASIP2 performs Fast Fourier Transform (FFT) to convert time domain signals to frequency domain signals for further processing. It supports FFT sizes from 4 to 8K.
    Block Diagram -- ASIP-2
  • FFT/IFFT Engine
    • Supports radix-2/3/4/5
    • Parametrized (radix, internal quantization, and FFT size)
    • Used as a building block for (I)FFTs and DFTs
    • Supports all LTE, WiMAX, DVB and xDSL standards
    Block Diagram -- FFT/IFFT Engine
  • Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs
    • FFT size: Any size power-of-two or non-power-of-two
    • Dynamic Range: IEEE754 single precision floating point
    Block Diagram -- Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs
  • N-Point FFT/IFFT
    • Parameterisable FFT block size
    • Parameterisable input signal width
    • Parameterisable internal scaling type (unscaled, scaled on every stage, optimised scaling)
    • Programmable input and output word lengths and internal precision
    Block Diagram -- N-Point FFT/IFFT
  • Non-Power-of-Two FFT
    • Sample Rates: Very high clock speeds
    • FFT size: any size set of transforms (chosen at run-time) factorable into bases up to ~10
    Block Diagram -- Non-Power-of-Two FFT
  • Fixed-size streaming FFT
    • High Throughput: obtained from high clock rates (>500MHz using 65nm technology) and novel algorithms
    • FFT size: Any size power-of-two or non-power-of-two
    • Dynamic Range: combined block floating point and floating point architecture means smaller word lengths can be used for post processing operations such as equalization (~6db/bit).
    • Scalability: array based architecture means higher throughputs are obtained by increasing array size
    Block Diagram -- Fixed-size streaming FFT
  • Variable FFT (run time choice of FFT size)
    • High Throughput: obtained from high clock rates (>500MHz using 65nm technology) and novel algorithms
    • FFT size: any user chosen set of power-of-two or non-power-of-two sizes chosen at run-time (e.g., 128/256/512/1024/2048 points for LTE/WiMax OFDMA)
    • Programmability: Simple control circuitry for matching circuit/application functionality and I/O interface.
    • Dynamic Range: combined block floating point and floating point architecture means smaller word lengths can be used for post-processing operations such as equalization.
    Block Diagram -- Variable FFT (run time choice of FFT size)
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