Introducing the next generation of AXI and ACE protocols
February 1, 2018
Arm is happy to announce the release of the next generation of AMBA 5 ACE5 and AXI5 protocols. A number of capabilities have been added over the prior AMBA 4 generation to align with AMBA 5 CHI. The protocols have been implemented in Arm’s latest technology including DynamIQ processers such as Cortex-A75 and Cortex-A55 along with the CoreLink CMN-600 Coherent Mesh Network.
To recap, here are the 3 main protocols included within the ACE and AXI specification:
- AXI (Advance Extensible Interface) – AXI provides connectivity for non-coherent masters and slaves
- ACE (AXI Coherency Extensions) – Supports full coherency for masters with caches such as Cortex-A processors.
- ACE-Lite – Supports IO coherency for masters without caches (Accelerators, IO, etc) that share coherent memory space.
To read the full article, click here
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- AXI Performance Subsystem - ARM Cortex A
- AHB Lite to AXI Bridge
- AXI 5-Master Component Low-Latency SRAM Controller
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