Introducing the next generation of AXI and ACE protocols
February 1, 2018
Arm is happy to announce the release of the next generation of AMBA 5 ACE5 and AXI5 protocols. A number of capabilities have been added over the prior AMBA 4 generation to align with AMBA 5 CHI. The protocols have been implemented in Arm’s latest technology including DynamIQ processers such as Cortex-A75 and Cortex-A55 along with the CoreLink CMN-600 Coherent Mesh Network.
To recap, here are the 3 main protocols included within the ACE and AXI specification:
- AXI (Advance Extensible Interface) – AXI provides connectivity for non-coherent masters and slaves
- ACE (AXI Coherency Extensions) – Supports full coherency for masters with caches such as Cortex-A processors.
- ACE-Lite – Supports IO coherency for masters without caches (Accelerators, IO, etc) that share coherent memory space.
To read the full article, click here
Related Semiconductor IP
- SPI Slave IP transfers to/from a AMBA APB, AXI, or AHB Interconnect
- 2D Graphics Hardware Accelerator (AXI Bus)
- SPI Slave To AXI Bridge IIP
- MIPI SPMI Slave AXI Bridge IIP
- MIPI I3C Slave To AXI Bridge IIP
Related Blogs
- How Google and Arm Collaborate on the Next Wave of Cloud Infrastructure
- Synopsys supports launch of Arm AMBA 5 AXI5, ACE5 protocols with 1st source code test suite and VIP
- A Strategy To Verify An AXI ACE Compliant Interconnect - Part 2 of 4
- A Strategy to Verify an AXI ACE Compliant Interconnect - Part 3 of 4