A Strategy to Verify an AXI ACE Compliant Interconnect - Part 3 of 4
February 11, 2013
In the last post of the series I wrote about basic coherent testing. In this post I will discuss some of the nuances of the specification relative to accesses to overlapping addresses. Since multiple masters may be sharing the same location and the data could be distributed across the caches of different masters, this is an important part of the verification of a coherent system. The interconnect plays a very important role in maintaining coherency for such accesses.
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Related Semiconductor IP
- Temperature Glitch Detector
- Clock Attack Monitor
- SoC Security Platform / Hardware Root of Trust
- SPI to AHB-Lite Bridge
- Octal SPI Master/Slave Controller
Related Blogs
- A Strategy To Verify An AXI ACE Compliant Interconnect - Part 2 of 4
- A Strategy to Verify an AXI/ACE Compliant Interconnect (2 of 4)
- Industry's First Source Code Test Suite and Verification IP for Arm AMBA ACE5 and AXI5 Enables Early Adopter Success
- Introducing the next generation of AXI and ACE protocols