A Strategy to Verify an AXI ACE Compliant Interconnect - Part 3 of 4
February 11, 2013
In the last post of the series I wrote about basic coherent testing. In this post I will discuss some of the nuances of the specification relative to accesses to overlapping addresses. Since multiple masters may be sharing the same location and the data could be distributed across the caches of different masters, this is an important part of the verification of a coherent system. The interconnect plays a very important role in maintaining coherency for such accesses.
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