How to use UML in your SoC hardware/software design: Part 3
Jul 31 2006 (9:30 AM), Embedded.com
Once you have captured the semantics of your SoC application model completely in a neutral form (see Part 2), you are now ready to compile it into software and silicon. Only the semantics of the modeling language matter for translation purposes.
If a class is represented graphically as a box, or even as text, this is of no consequence. The UML is just an accessible graphical front-end for those simple elements.
When you build a 'class' such as CookingStep in a microwave oven, that represents a set of possible cooking steps you might execute, each with a cooking time and power level.
Similarly, when you describe the lifecycle of a cooking step using a state machine, it follows a sequence of states as synchronized by other state machines, external signals, and timers. And in each state, we execute some functions. All of this structure and behavior, for the entire model, is captured as data in the metamodel.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related White Papers
- How to manage changing IP in an evolving SoC design
- How to reuse your IIoT technology investments - now
- How to use snakes to speed up software without slowing down the time-to-market?
- How a voltage glitch attack could cripple your SoC or MCU - and how to securely protect it
Latest White Papers
- New Realities Demand a New Approach to System Verification and Validation
- How silicon and circuit optimizations help FPGAs offer lower size, power and cost in video bridging applications
- Sustainable Hardware Specialization
- PCIe IP With Enhanced Security For The Automotive Market
- Top 5 Reasons why CPU is the Best Processor for AI Inference