EDA needs functional qualification

Verification is a very expensive activity in integrated circuit (IC) development. It is also a difficult activity to complete efficiently. Coverage-driven verification (CDV) has been widely adopted in the industry, but is also widely accepted as being an incomplete measurement of verification.

To find a design bug, three things must occur during the execution of the verification environment:

1. The bug must be activated, i.e., the code containing the bug must be exercised.
2. The bug must be propagated to an observable point, e.g., the outputs of the design.
3. The bug must be detected, i.e., behavior checked and a failure indicated.

Techniques such as code coverage and functional coverage can help ensure that design code is activated. However, they cannot guarantee that design bugs will be propagated, nor that they will be detected by the checkers and/or assertions.

The verification environment must exercise a path through the design (from inputs to checkers) and these temporal inter-process relationships are not present in code coverage information. It is quite possible that code will be covered only as an unintended side effect of a test case. Code coverage can indicate that code has been exercised during simulation, but this does not tell the user if a bug in the same code would propagate to a checker and cause a test case to fail. Furthermore, code coverage does not indicate if the output behavior is being checked correctly.

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