Medium throughput, compact Reed Solomon decoder

Overview

This implementation of a M=8 Reed Solomon decoder has been designed to use a minimum set of resources whilst maintaining a medium throughput and flexible configuration. It supports per-packet setting for codeword length, message length, generator polynomial start index and fully supports the maximum number of erasures. It requires 16k gates and one 8x256 bit single port synchronous SRAM. The clock frequency needs to be 3x the message bit rate. The core benefits from an APB interface for setup and control, plus an AXI4-Stream master slave interface for the data plane. The AXI4-Stream interface fully supports bursty input data and backpressure on the output.

Key Features

  • Per-packet setting of
    • message length
    • codeword length
    • generator start index
  • Fully supports erasures
  • APB control interface with interrupt after processing packets
  • AXI4-Stream data interface.
  • Verilog 2001
  • Fully synchronous

Benefits

  • Low resource requirement
  • Medium throughput
  • Easy interfacing

Deliverables

  • RTL
  • Testbench
  • Synthesis scripts
  • Documentation
  • MATLAB and C++ bit exact mode

Technical Specifications

Foundry, Node
Any
Availability
Now
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Semiconductor IP