JESD204B PHY & Controller

Overview

JESD204B is a standardized serial interface for communication between logic devices (ASIC or FPGA) and converters (ADC or DAC). Innosilicon’s JESD204B Core provides high interoperability between devices, with serial data rate up to 12.5Gbps per lane. Featuring multi-converter alignment and multi-channel support, it is designed to improve power efficiency and simplify PCB routing. It contains the information necessary to offer standard transmission and interconnection transmission with user’s IRU components that are compliant with the standard.

Key Features

Support for serial data rates up to 12.5Gbps
Supports Subclass 0, 1 and 2.
Supports 4 lanes.
Supports 1-32 converters.
Supports HD-mode.
Supports user-enabled scrambling.
Supports 8b/10b encoding/decoding.
Generates initial lane alignment sequence.
Supports SCAN mode.
Supports BIST(PHY)mode
Support interconnected transmission with user’s IRU components

Benefits

As with all Innosilicon IP, the focus is on silicon proven, fully certified solutions providing:
Small size
Low power
High ATE coverage
Simple integration
Flexible customization

Deliverables

Verilog Sim Behavioral simulation model for the PHY
Encrypted IO spice netlist for SI evaluation
Integration Guidelines
Test Guidelines
GDSII Layout and layer map for foundry merge
Place and Route LIB and LEF views for the AFE
LVS and DRC verification reports

Technical Specifications

Foundry, Node

GF 22nm, SMIC 28nm

Maturity

Silicon proven and validated

GLOBALFOUNDRIES

In Production: 22nm
Pre-Silicon: 28nm SLP
Silicon Proven: 22nm

SMIC

In Production: 28nm
Silicon Proven: 28nm

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