Error Correction/Detection IP

Compare 245 Error Correction/Detection IP from 40 vendors (1 - 10)

VESA DisplayPort 2.0 FEC RX
- VESA DisplayPort 2.0 compliant
- Reed Solomon RS (198,194) FEC, 8-bit symbols
- Multiple symbols per clock
VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
- Complete DisplayPort™ 1.4 Receiver solution with support for VESA Display Stream Compression (DSC)
HDMI 2.1 Forward Error Correction (FEC) Receiver
- HDMI 2.1 compliant
- Reed-Solomon RS(255,251) FEC, 8-bit symbols
- Supports 3-lane and 4-lane operation
LDPC Encoder/Decoder (LDPC)
- Supporting a wide range of data-rates
- 50MB/s to 4.0GB/s for a single LDPC instance
- Scalable platform provides the basis for customer specific custom-LDPC cores
Viterbi Decoder
- Hard or soft decoder with configurable soft bit widths
- Parameterisable generator polynomials
- Parameterisable code Constraint length
LDPC Decoder for 5G NR and Wireless
- Feature rich, highly flexible, scalable, configurable and timing friendly design
- Ease of integration
- Compliance with 3GPP Standards
Polar Encoder / Decoder for 3GPP 5G NR
- Fully compliant with the 3GPP NR standard for PUCCH, PUSCH, PDCCH and PBCH. Supports the full range of uncoded and encoded block sizes
- Implements the entire Polar encoding and decoding chain in 3GPP TS38.212
- High error correction performance from Polar PC/CRC-aided decoder core
- Tightly integrates the components in the chain to reduce area usage and latency
LDPC Encoder / Decoder for 3GPP 5G NR
- Fully compliant with the 3GPP NR standard for PDSCH, PUSCH. Supports the full range of uncoded and encoded block sizes
8b/10 Decoder
- 8b10b decoding
- Can be cascaded for 16b20b decoding
- Supports industry standard comma “K” symbols
- Pipelined design
Reed Solomon Encoder
- Parameterizable bits per symbol
- Programmable codeword length
- Programmable number of errors