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576
Broadcast IP
from 99 vendors
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IP cores for ultra-low power AI-enabled devices
- Ultra-fast Response Time
- Zero-latency Switching
- Low Power
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VESA DisplayPort 2.0 FEC RX
- VESA DisplayPort 2.0 compliant
- Reed Solomon RS (198,194) FEC, 8-bit symbols
- Multiple symbols per clock
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VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
- Complete DisplayPort™ 1.4 Receiver solution with support for VESA Display Stream Compression (DSC)
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HDMI 2.1 Forward Error Correction (FEC) Receiver
- HDMI 2.1 compliant
- Reed-Solomon RS(255,251) FEC, 8-bit symbols
- Supports 3-lane and 4-lane operation
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LDPC Encoder/Decoder (LDPC)
- Supporting a wide range of data-rates
- 50MB/s to 4.0GB/s for a single LDPC instance
- Scalable platform provides the basis for customer specific custom-LDPC cores
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Tessent RISC-V trace and debug
- Instruction trace
- Efficient packet format
- Fast profiling
- Multiple retirement
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Multi Channel FIR Filter
- Multi Channel FIR filter
- Selectable data and coefficient widths
- Selectable number of data channels
- Selectable number of filter taps
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Viterbi Decoder
- Hard or soft decoder with configurable soft bit widths
- Parameterisable generator polynomials
- Parameterisable code Constraint length
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LDPC Decoder for 5G NR and Wireless
- Feature rich, highly flexible, scalable, configurable and timing friendly design
- Ease of integration
- Compliance with 3GPP Standards
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Merge Sort Core
- Optimized design allows customers to target cost efficient FPGAs.
- Can be tailored to customer needs
- Fully synchronous design using only one clock
- Area/Power efficient architecture
