The core maps a memory device connected via the Serial Peripheral Interface (SPI) into AMBA AHB address space. Reading memory is performed by directly accessing the memory using reads on a AHB slave interface. Other operations, e.g. writes, are performed by sending SPI commands using the core's register interface. The SPIMCTRL supports most SPI Flash devices.
The SPIMCTRL can be configured to support a wide range of SPI instruction types/protocols through the Quadinput, Dualinput, Quadoutput, Dualoutput, DSPI and QSPI bits.
The SPIMCTRL is inherently portable and can be implemented on most FPGA and ASIC technologies.
The SPIMCTRL core can be licensed under the GPL or a commercial license as part of the GRLIB IP library.
QUAD SPI Memory controller
Overview
Deliverables
- VHDL source code
- User's manual
Technical Specifications
Related IPs
- Single, Dual and Quad SPI Flash Controller with Boot and Execute On-The-Fly Features
- Avalon Multi-port DDR2 Memory Controller
- AXI Quad SPI
- Serial Peripheral Interface - Master/Slave with single, dual and quad SPI Bus support
- Quad SPI Controller
- Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support