SDRAM Synthesizable Transactor provides a smart way to verify the SDRAM component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's SDRAM Synthesizable Transactor is fully compliant with standard 512Mb_sdr & HY57V56820FT-H.pdf Specification and provides the following features.
SDRAM Synthesizable Transactor
Overview
Key Features
- Supports 100% of SDRAM protocol standard 512Mb_sdr & HY57V56820FT-H
- Supports internal banks for hiding row access/precharge
- Supports programmable burst lengths: 1, 2, 4, 8, or full page
- Supports auto precharge, includes concurrent auto precharge and auto refresh modes
- Supports self refresh mode
- Supports auto refresh
- Supports programmable clock frequency of operation
- Supports all types of timing and protocol violation detection
- Supports all mode registers programming
- Supports speed grade:
- 7E
- 75
- Supports all the SDRAM commands as per the 512Mb_sdr & HY57V56820FT-H
- Checks for following:
- Check-points include power on, initialization and power off rules
- State based rules, active command rules
- Read/Write commands rules etc
- All timing violations
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
Block Diagram
Deliverables
- Synthesizable transactors
- Complete regression suite containing all the SDRAM testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes