GCI Synthesizable Transactor

Overview

The GCI Synthesizable Transactor is compliant with V1.0 specifications and verifies GCI interfaces. GCI is build on top of it to make it robust. GCI Synthesizable Transactor provides a smart way to verify the GCI component of a SOC or a ASIC in Emulator or FPGA platform. GCI Synthesizable Transactor is developed by experts in networking, who have developed networking products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a networking product.

Key Features

  • Compliant to GCI protocol specification v1.0
  • Supports fixed-sized frames
  • Supports configurable number of serial lanes as per the specification
  • Supports 10 bit per lane serdes interface
  • Supports training sequence as per spec
  • Reset the data link layer
  • Supports configurable Tx and Rx long term CRC function per lane
  • Supports CID and Idle/Pause frames
  • Supports Scrambler as per spec
  • Supports lane reordering as per spec
  • Supports breaking of frames into sub-frames
  • Supports replay and error recovery
  • Supports polarity inversion
  • Supports Per lane skew insertion to test lane alignment
  • Supports Addressable registers
  • Supports very flexible way to test sync and alignment for state machines at startup
  • Recovers clock from input serial data stream
  • Supports all types of error insertion and detection
    • CRC errors
    • Pause frame errors
    • Bad scrambler state
    • Lane alignment failure
    • Disparity errors
    • Invalid code group insertion
    • Invalid /K/ characters insertion
    • Lane Skew insertion

    Benefits

    • Compatible with testbench writing using SmartDV's VIP
    • All UVM sequences/testcases written with VIP can be reused
    • Runs in every major emulators environment
    • Runs in custom FPGA platforms

    Block Diagram

    GCI Synthesizable Transactor
 Block Diagram

    Deliverables

    • Synthesizable transactors
    • Complete regression suite containing all the GCI testcases
    • Examples showing how to connect various components, and usage of Synthesizable Transactor
    • Detailed documentation of all DPI, class, task and functions used in verification env
    • Documentation contains User's Guide and Release notes

    Technical Specifications

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Semiconductor IP