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Transform IP

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Compare 44 Transform IP from 15 vendors (1 - 10)
  • Fully Configurable Radix 2 FFT/IFFT Processor
    • Radix-2 Fast Fourier Transform processor IP Core.
    • Same IP core may be used to compute both FFT and IFFT transforms without any complexity overhead.
    • Highly parameterizable/scalable design using generic I/O fixed point precision and generic internal calculations precision.
    • Bit true Matlab script model is provided to aid core fixed point precision configuration for any target application.
    Block Diagram -- Fully Configurable Radix 2 FFT/IFFT Processor
  • Interleaver / De-interleaver
    • Support for block or convolutional (de interleaving algorithm.
    • Programmable interleaving or deinterleaving functionality.
    • Parameterized symbol width and codeword length.
    • Programmable block size, number or rows/columns.
    Block Diagram -- Interleaver / De-interleaver
  • MIMO Radar Co-processor Engine
    • Low latency, low power and compact
    • Gives ECU headroom for track-to-object recognition and make safety decisions
    Block Diagram -- MIMO Radar Co-processor Engine
  • 32-512 Point Streaming FFT
    • Supports 32/64/128/256/512-point complex FFT and IFFT and can switch dynamically
    • Inputs and outputs data in the natural order
    • Throughput of 1 sample (In-phase I + quadrature Q) per 4 clocks; no-gap processing of the input data
    • Parameterized bit width.
    Block Diagram -- 32-512 Point Streaming FFT
  • ASIP-2
    • Platform to design Application Specific Instruction Set Processors (ASIPs).
    • Ideal for supporting multi-standard systems.
    • Supports a wide range of complex DSP functions.
    • The ASIP2 performs Fast Fourier Transform (FFT) to convert time domain signals to frequency domain signals for further processing. It supports FFT sizes from 4 to 8K.
    Block Diagram -- ASIP-2
  • FFT/IFFT Engine
    • Supports radix-2/3/4/5
    • Parametrized (radix, internal quantization, and FFT size)
    • Used as a building block for (I)FFTs and DFTs
    • Supports all LTE, WiMAX, DVB and xDSL standards
    Block Diagram -- FFT/IFFT Engine
  • Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs
    • FFT size: Any size power-of-two or non-power-of-two
    • Dynamic Range: IEEE754 single precision floating point
    Block Diagram -- Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs
  • Image Stabilization IP Core
    • Max video frame size - 1024x1024 pixels.
    • Min video frame size - 128x128 pixels.
    Block Diagram -- Image Stabilization IP Core
  • Automatic Video Tracking IP Core
    • Maximum and minimum sizes of tracking strobes - The maximum size of tracking strobe is 128x128 pixels. The minimum size of tracking strobe is 16x16 pixels. The strobe size can be set separately for each object, both before object capture for tracking and during tracking.
    • Number of tracking channels - 5 independent tracking chanels.
    • Maximum size of tracking object - Maximum size of the tracking object is limited by maximum size of the tracking strobe (128x128 pixels).
    • Minimum size of tracking object - The core ensures stable tracking of objects of up to 8x8 pixels size.
    Block Diagram -- Automatic Video Tracking IP Core
  • N-Point FFT/IFFT
    • Parameterisable FFT block size
    • Parameterisable input signal width
    • Parameterisable internal scaling type (unscaled, scaled on every stage, optimised scaling)
    • Programmable input and output word lengths and internal precision
    Block Diagram -- N-Point FFT/IFFT
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