The AMBA AXI4 Verification IP provides an effective & efficient way to verify the components interfacing with AMBA® AXI4 bus of an IP or SoC. The AMBA AXI4 VIP is fully compliant with standard AMBA® AXI4 specification from ARM. This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design cycle time.
AMBA AXI4 Verification IP
Overview
Key Features
- Compliant to AMBA® AXI4 specifications from ARM and
- supports for all variants of AXI4, AXI4-Lite and AXI4 Stream.
- Support for all type of AMBA AXI4 devices.
- Strong protocol checking Bus Monitor which also provides statistics of the transactions.
- Parameterized data and address bus.
- Supports for all protocol Burst Types, Burst Lengths and Response Types.
- Configurable modes for Valid and Ready on different channels.
- Rich set of configuration parameters to control AXI4 functionality.
- Supports FIFO, memory and Cache Model integrated.
- Supports Privilege and Secure accesses.
- Supports out of order transactions with parametrized out of order width.
- Supports data interleaving on read data channel.
- Supports Endianess check and conversion.
- Supports exclusive transfers and configurable Memory.
- Supports UVM_RAL Model.
- Provides detailed performance monitoring for all the transfers.
- Supports advanced SystemVerilog features like constrained random testing.
- Supports dynamically configurable modes.
- Strong Protocol Monitor with real time exhaustive programmable checks.
- Supports Dynamic as well as Static Error Injection scenarios.
- On the fly protocol checking using protocol check functions, static and dynamic assertion.
- Built in Extensive Coverage Across the Channels.
- Provides a comprehensive user API (callbacks) in all BFMs.
- Graphical analyser to show transactions for easy debugging.
Block Diagram
