Using Cache Coherency to Verify the AMBA4 Protocol
January 4, 2012
The Jasper User Group Meeting was held on November 8 & 9 and was full of presentations on the diverse ways that users are applying formal techniques – some in areas where never before thought possible. Paul Martin from ARM was one of those users who presented on this topic. ARM discussed how modern multi-core processors now require much more sophisticated cache control than before, ensuring that all devices in the system have the same view of shared data, known as cache coherency. ARM in particular has created some quite sophisticated protocols, AXI Coherency Extensions (ACE), under the AMBA 4 umbrella, that they announced at DAC.
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