Is the System on Chip Coming Apart?
Arguably it is, in some circumstances. This disintegration can take any of several paths—some of which wind deep into the promising yet problematic technology of 2.5D packaging, while others lead back to the seemingly archaic landscape of separate chips on a board, albeit with very unarchaic interconnect technology. The only accurate map for these varied routes will spring from the architect’s skill at system partitioning.
At least that is the story told by a number of the plenary talks and technical paper sessions at this year’s International Solid State Circuits Conference (ISSCC). This conference, which has for years charted the inexorable Moore’s-Law advance of integration, now appears, ironically, to be signaling an inflection point that could lead system design back toward discrete multi-chip implementations.
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