Further Targeted Design Platform adventures
December 9, 2009
When Xilinx first launched its Targeted Design Platform concurrent with Virtex-6 sampling early this year, the only question seemed to be whether vertical-market configurations could be developed as quickly as FPGAs took over new markets. We can give the TDP development team an ‘A’ for effort, but the Dec. 8 announcement of new TDPs spotlights the mad scramble vendors must undertake to serve users.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related Blogs
- TSMC Open Innovation Platform Explained
- TSMC Extends Open Innovation Platform
- Plunify launches SaaS platform that integrates FPGA design tools
- Is the Common Platform Alliance a credible competitor to TSMC?
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?