RiVer Core: A RISC-V Core Verification Framework

By _InCore Semi Blog

July 1, 2021

InCore and Tessolve announce the availability of our open source RISC-V Core Verification tool - RiVer Core. RiVer Core is a python based extensible and scalable framework aimed at providing a central control point for all major aspects of a RISC-V processor verification flow. The tool is fully open source under the permissive BSD-3 Clause License.

The repository is hosted on Github - https://github.com/incoresemi/river_core

RiVer requires 3 major components to a RISC-V Core.

1. A set of tests which need to be run on the target. These could be either random or directed in nature.
2. A RISC-V target that needs to be tested. This is typically an RTL implementation, but could also include other micro-architectural models
3. A Reference model against which checks are performed to determine pass/fail conditions.

Through the RiVer Core framework, you can continue to build and generate new tests using an existing environment and scripts independently of the environment chosen/used by the target or the reference. Similarly, you can easily replace the reference models for different tests depending on the test's requirements. Unlike other conventional frameworks, RiVer takes a more holistic approach and avoids creating any environment tailored to a specific test-suite, target environment or reference environment, thereby allowing use of RiVer in existing environments.

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