MIPI LLI or C2C?
January 18, 2012
Two new options for interchip connectivity are available today that enable sharing a DRAM memory between two chips for data and programs. These standards, called MIPI Low Latency Interface (MIPI LLI) and Chip-to-Chip (C2C), are primarily targeted at mobile phones, where a mobile phone’s modem usually requires its own discreet DRAM. With either C2C or MIPI LLI, the mobile phone modem can use the application processor’s DRAM though a low-latency, memory-mapped connection that requires no software drivers or runtime software.
Related Semiconductor IP
- MIPI MPHY v3.1, 1Tx-1Rx Type-1, SMIC 40LL, N/S orientation
- MIPI MPHY v3.1, 2Tx-2Rx Type-1, UMC 22ULL 1.8V, N/S orientation
- MIPI MPHY v3.1, 1Tx-1Rx Type-1, TSMC 55LP,
- MIPI MPHY v3.1, 2Tx-2Rx Type-1, TSMC 28HPC+, N/S orientation
- MIPI MPHY v3.1, 2Tx-2Rx Type-1, TSMC 16FFC, N/S orientation(ASIL-B)
Related Blogs
- TI OMAP 5 Platform includes MIPI LLI and C2C interchip connectivity
- Interchip Connectivity: C2C, MIPI LLI and the path to 3D IC and TSV
- Interface Standards Table - MIPI HSI, HSIC, UniPro, UniPort, LLI, C2C
- SLD article on Interchip Connectivity: HSIC, HSI, C2C, LLI... oh my!
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