MIPI LLI or C2C?
January 18, 2012
Two new options for interchip connectivity are available today that enable sharing a DRAM memory between two chips for data and programs. These standards, called MIPI Low Latency Interface (MIPI LLI) and Chip-to-Chip (C2C), are primarily targeted at mobile phones, where a mobile phone’s modem usually requires its own discreet DRAM. With either C2C or MIPI LLI, the mobile phone modem can use the application processor’s DRAM though a low-latency, memory-mapped connection that requires no software drivers or runtime software.
To read the full article, click here
Related Semiconductor IP
- MIPI D-PHY Universal IP in UMC 28HPC+
- MIPI C/D Combo TX PHY and DSI controller
- MIPI D-PHY TX PHY and DSI controller
- MIPI CD PHY Combo TX & RX + DSI & CSI Controller
- MIPI D-PHY TX & RX + DSI & CSI Controllers
Related Blogs
- TI OMAP 5 Platform includes MIPI LLI and C2C interchip connectivity
- Interchip Connectivity: C2C, MIPI LLI and the path to 3D IC and TSV
- Interface Standards Table - MIPI HSI, HSIC, UniPro, UniPort, LLI, C2C
- SLD article on Interchip Connectivity: HSIC, HSI, C2C, LLI... oh my!
Latest Blogs
- Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
- The Industry’s First USB4 Device IP Certification Will Speed Innovation and Edge AI Enablement
- Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
- 2025 Outlook with Mahesh Tirupattur of Analog Bits
- eUSB2 Version 2 with 4.8Gbps and the Use Cases: A Comprehensive Overview