SLD article on Interchip Connectivity: HSIC, HSI, C2C, LLI... oh my!
April 1, 2011
There has been a lot of confusion about LLI C2C specifications resized 600the different standards for interchip connectivity, with many hardware developers of consumer electronics and mobile computing systems-on-chip wondering what to use. As an interconnect IP provider, I struggle with this every day when working with our customers. I wrote this article to share what I have learned.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related Blogs
- TI OMAP 5 Platform includes MIPI LLI and C2C interchip connectivity
- Interchip Connectivity: C2C, MIPI LLI and the path to 3D IC and TSV
- Interface Standards Table - MIPI HSI, HSIC, UniPro, UniPort, LLI, C2C
- MIPI LLI or C2C?
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?